Which register holds the address of the next instruction to be fetched in the fetch-execute cycle?

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Multiple Choice

Which register holds the address of the next instruction to be fetched in the fetch-execute cycle?

Explanation:
In the fetch-execute cycle, the next instruction to be fetched is located by the Program Counter. This register always holds the memory address of the instruction that should be read next. After each fetch, the PC is typically incremented to point to the subsequent instruction, ensuring the CPU processes instructions in sequence. While the Memory Address Register may hold memory addresses during the actual access, the specific role of pointing to the next instruction is the Program Counter. The data bus is about moving data, not storing addresses, and a vague “register” doesn’t specify the needed function.

In the fetch-execute cycle, the next instruction to be fetched is located by the Program Counter. This register always holds the memory address of the instruction that should be read next. After each fetch, the PC is typically incremented to point to the subsequent instruction, ensuring the CPU processes instructions in sequence. While the Memory Address Register may hold memory addresses during the actual access, the specific role of pointing to the next instruction is the Program Counter. The data bus is about moving data, not storing addresses, and a vague “register” doesn’t specify the needed function.

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